The present invention relates generally to integrated circuit chip package technology and, more particularly, to a unique fan-in leadframe design for a semiconductor package which provides a reduced land footprint thus improving solder joint reliability, and further simplifies motherboard routing due to the availability of free space under the semiconductor package outside of the land pattern.
Integrated circuit or semiconductor dies are conventionally enclosed in plastic packages that provide protection from hostile environments and enable electrical interconnection between the semiconductor die and an underlying substrate such as a printed circuit board (PCB) or motherboard. The elements of such a package include a metal leadframe, a semiconductor die, bonding material to attach the semiconductor die to the leadframe, bond wires which electrically connect pads or terminals on the semiconductor die to individual leads of the leadframe, and a hard plastic encapsulant material which covers the other components and forms the exterior of the package often referred to as the package body.
The leadframe is the central supporting structure of such a semiconductor package. A portion of the leadframe is internal to the package, i.e., completely surrounded by the plastic encapsulant. Portions of the leads of the leadframe extend externally from the package or are partially exposed within the encapsulant material for use in electrically connecting the package to another component.
In certain semiconductor package designs, the bottom surface of each of the leads of the leadframe is exposed within the bottom surface of the package body formed by the hardening of the encapsulant material. In this design, solderable surfaces are provided on only the bottom surface of the package body and, more particularly, by the exposed bottom surfaces of the leads which are often referred to as lands. This type of semiconductor package is typically attached to the printed circuit board or motherboard by printing solder paste on the board, positioning the exposed bottom surfaces of the leads upon the solder paste, and completing a hot reflow process.
One major drawback associated with the above-described semiconductor package design is the relatively large land footprint which results in certain situations, such as when a large semiconductor die is integrated into the package. This increased land footprint causes increased stress in the solder joints during temperature cycling and further complicates motherboard routing due to the increased amount of space needed to accommodate the semiconductor package. The present invention eliminates this deficiency by providing a semiconductor package having a fan-in leadframe and adapted to accommodate a large semiconductor die. The fan-in semiconductor package of the present invention provides a reduced land footprint, thereby improving solder joint reliability due to a reduction in stress on solder joints during temperature cycling. The reduced land footprint also allows for easier motherboard routing due to free space being available under the semiconductor package outside of the land pattern. These, as well as other features and advantages of the present invention, will be discussed in more detail below.